1. Field of the Invention
The present invention relates to a serial-parallel conversion apparatus and in particular, to a data demultiplexer (DEMUX) circuit used in a serial-parallel conversion circuit for use in an optical communication system and a serial-parallel conversion circuit using the data demultiplexer circuit.
2. Description of the Related Art
FIG. 5a shows a tree-type serial to parallel conversion (demultiplexer) circuit used as a circuit for converting a parallel signal into a signal transmitted in serial in an optical communication or the like. This circuit includes an edge trigger type flip-flop (D-FF) (FIG. 5b) operating at a clock signal rise timing and a Master-Slave-Master type flip-flop (MSM-FF) (FIG. 5c) using three latch circuits to fetch a data at a clock signal trail timing and hold the data for one clock cycle starting at the next clock rise timing. This demultiplexer circuit divides a signal by two at each stage so as to reduce the frequency to half.
That is, at stage S1 shown in FIG. 5a, a data (Data in) is supplied as a D input to an MSM-FF 10-11 and a D-FF 11-11 and a reverse Q output of the D-FF 12-1 is supplied as a D input to a D-FF 12-1 for dividing a clock signal CLK. The clock signal CLK (2 GHz) is inputted directly to the MSM-FF 10-11 and to the D-FF 11-11.
Moreover, at stage S2 in FIG. 5a, the Q output from the MSM-FF 10-11 is supplied as the D input to an MSM-FF 10-21 and a D-FF 11-21; the Q output from the D-FF 11-11 is supplied as the D input to an MSM-FF 10-22 and a D-FF 11-22; and the Q output from the D-FF 12-1 is divided by a D-FF 12-2.
The clock signal CLK which has been divided by the D-FF 12-1 is supplied as a clock signal (1 GHz) to the MSM-FF 10-21, the D-FF 11-21, the MSM-FF 10-22, and the D-FF 11-22.
Furthermore, at stage S3 in FIG. 5A, the Q output from the MSM-FF 10-21 is supplied as the D input to an MSM-FF 10-31 and a D-FF 11-31; the Q output from the D-FF 11-21 is supplied as the D input to an MSM-FF 10-32 and a D-FF 11-32; the Q output from the MSM-FF 10-22 is supplied as the D input to an MSM-FF 10-33 and a D-FF 11-33; and the Q output from the D-FF 11-22 is supplied as the D input to an MSM-FF 10-34 and a D-FF 11-34.
The clock signal (1 GHz) is further divided by the D-FF 12-2, and a resultant clock signal (500 MHz) is supplied to each of the MSM-FF 10-31 to 10-34 and each of the D-FF 11-31 to 11-34. It should be noted that the clock signal (500 MHz) obtained as a result of dividing by the D-FF 12-2 is outputted together with 8-bit parallel data D0 to D7 which are outputted from the MSM-FF 10-31 to 10-34 and the D-FF 11-31 to 11-34, respectively.
The tree-type serial-parallel conversion circuit shown in FIG. 5 has a problem that the circuit size becomes greater than a typical shift-register-type demultiplexer circuit. Moreover, there is a problem that it is impossible to correlate a serial input signal to an output signal. For example, it is impossible to know a signal of which timing is outputted from the terminal D0. In spite of these problems, there is an advantage that the necessary clock frequency is sufficient to be half of the input signal cycle. (For example, for a 4 Gbps data signal, a clock of 2 GHz is sufficient.) Accordingly, the tree-type serial-parallel conversion circuit is now widely used as a high-speed demultiplexer circuit of CMOS (complementary metal oxide semiconductor).
It should be noted that the MSM-FF is constituted by three latch circuits connected in series. A clock signal is directly inputted to a first stage latch circuit and to a third stage latch circuit, whereas the clock signal is reversed when supplied to a second stage latch circuit.
The circuit configuration of FIG. 5 has a problem that the clock signal dividing circuits are spatially separated from the demultiplexer circuit block (D-FF and MSM-FF). This requires a great effort in design and production, so as to adjust a timing between a clock signal and a data signal.